1. Field of the Invention
The invention concerns a fast analog/digital converter with a parallel structure.
2. Description of the Prior Art
The term "analog/digital converter with parallel structure" refers to a converter such as the one shown in FIG. 1.
To obtain fast conversion, the converter has 2.sup.n comparators identical to the comparator 10, working in parallel, n being the number of converter output bits. Each comparator receives, firstly, the analog voltage Vin to be converted into a binary digital value of n bits and, secondly, a respective reference voltage which is a fraction, expressed in multiples of 1/2.sup.n, of a general reference voltage Vref. Thus, for example, for an eight-bit converter (2.sup.8 =256), the first converter receives Vref/256 as the reference voltage, the second comparator receives 2Vref/256, the third comparator receives 3Vref/256, etc. up to the last comparator which receives Vref.
Each of the comparators gives a binary output logic level indicating whether the voltage Vin is greater or smaller than its respective reference voltage.
The outputs of all the comparators are applied to a logic decoding circuit 20. This decoding logic circuit 20 thus receives 2.sup.n logic signals which, if examined successively, are in the form of a series of logic signals with a first level (for all those comparators for which the reference voltage is smaller than the voltage to be converted), followed by a series of logic signals with a second level (for all the other comparators). The decoding circuit determines the position of the change in logic level in this dual series and gives an n-bit word representing this position or, as the case may be, an indication that the capacity of the converter has been exceeded.
The reference voltages are set up by means of a high-precision resistive divider bridge, formed by 2.sup.n series-mounted resistors with a common value R and powered by the overall reference voltage Vref. An intermediate connector is provided at each junction point of two resistors R, and this connector is connected to an input of a respective comparator to bring it a corresponding reference voltage which is a fraction that is a multiple of 1/2.sup.n of Vref.
FIG. 1 gives a schematic view of an eight-bit converter. The reference voltages are designated by V1, V2 . . . Vr, . . . V255, Vref. A single comparator 10 has been shown, receiving a reference voltage Vr.
In integrated circuit technology, low voltages are used and the reference voltage Vref may not exceed two volts. Consequently, the elementary pitch between two consecutive reference voltages is 2/256 volts, giving about eight millivolts. It is therefore imperative to use, as comparators, differential amplifiers with very low offset voltage at the input, failing which the comparison would make no sense.
This is why use is made of comparators associated with a capacitor which memorizes the offset voltage and restores it by adding it to the difference between the voltages to be compared, in such a way that the flip-over of the comparator results only from the sign of this difference, irrespectively of the value of the offset voltage.
The single comparator 10, shown in FIG. 1, is a comparator of this type, with elimination of offset voltage. It has an amplifier-inverter 12, an input capacitor C of which one terminal is connected to the input of the amplifier and of the change-over switching means (switches IE, IE', IC which may be insulated-gate field-effect transistors) controlled by a control logic circuit (not shown).
The switch IE can be used to connect the reference voltage Vr, corresponding to this comparator, to the other terminal of the capacitor C;
The switch IE' can be used to connect the analog voltage Vin to be converted to the other terminal of the capacitor C;
The switch IC can be used to set up a short-circuit feedback loop of the amplifier 12 with its input.
The change-over control logic circuit works cyclically in essentially two stages.
In a first stage a, the switch IE is shut; outside this stage it stays open.
In a second stage c, the switch IE' is shut; outside this stage, it stays open. In practice, the stages a and c are complementary.
Within one of these stages, in practice during a stage b which essentially coincides with the first stage a but which must imperatively end slightly before it, the switch IC is shut. If need be, the stage b could coincide with the stage c and not the stage a.
In practice, the stage b coincides with the stage a. The stage a is applied to all the comparators at the same time so that the capacitor C of each comparator takes a load C (Vr-Vs), Vs being the offset voltage of the inverter 12. This stage therefore makes it possible to take each inverter 12 into account. This stage is conventionally called an auto zero stage.
Quite clearly, this stage must be applied to all the comparators before the voltage Vin to be converted is applied, said voltage being applied during the stage c. Thus, each comparator is ready to receive the voltage Vin and flips over or does not flip over, without any deterioration due to the initial conditions in which it is placed when this voltage Vin is applied.
Fresh problems now face the specialist who is seeking to make fast converters with higher resolution than that obtained by existing converters. For, the specialist encounters difficulties in making the device as soon as he seeks to obtain converters with more than 8 bits, particularly in MOS technology.
The usual approach is, firstly, to increase the speed of the converters, to increase the size of the transistors which fulfill the inverter function. Now, this increase in size causes an increase in current consumption which is not bothersome in itself but becomes bothersome when, in addition to this, there is an increase in consumption due to an increase in the number of comparators. For, during the stage b (which, in practice, corresponds to the stage a), the switch C is closed for all the comparators. These comparators are thus connected in feedback loops with unitary gain. This corresponds to their maximum consumption point, and this consumption is all the higher as the bits, comprising:
a reference voltage generator; PA1 2.sup.n comparators capable of comparing the analog voltage with a reference voltage, each comparator comprising an inverter amplifier, a capacitor having a first terminal connected to the input of the amplifier; PA1 change-over switching means and a control logic circuit for these means working cyclically according to the following cycle: PA1 wherein at a given instant, one or more comparators are in the first stage (a) while all the other converters are in the second stage (c); so that, successively, each comparator goes through this first stage while the other comparators are in the second stage (c); PA1 and the control logic circuit has means to generate clock signals to sequence the passage of each comparator in the first stage (a) and then in the second stage (c) by the activation of change-over switching means, said converter comprising means to decode the signals given by the comparators.
during a first stage (a) of each cycle, the amplifier is in short-circuit feedback loop, while the reference voltage is applied to the other terminal of the capacitor; PA2 during a second stage (c), the amplifier is no longer connected in short-circuit feedback loop, and the analog voltage is applied to the other terminal of the capacitor;
Another object of the invention is the making of an analog/digital converter wherein the reference voltage generator is made by means of a precision resistors bridge.
Another object of the invention is the making of an analog/digital converter wherein the voltage generator is formed by a digital/analog converter with m bits, m being greater than n, said converter being driven by a digital counter driven by the clock signal generating means. Another object of the invention consists in the making of an analog/digital converter in which the clock signal generating means are formed by a shift register, the output of which drives the input and which is controlled by an external clock.
Another object of the invention is an analog/digital converter wherein the decoding means have 2.sup.n flip flops, each receiving the output signal of a comparator and delivering this signal at the rate of an external clock, the output result of each flip flop being forced into a given state when this flip flop is connected to a comparator which is in the stage a of operation (auto zero) while all the others are in the stage c. comparators are faster and more sensitive. Furthermore, during the stage b, the 2.sup.n comparators and 2.sup.n capacitors are connected to the bridge of resistors. Firstly, this introduces dynamic disturbances on the bridge, and the bridge cannot recover its initial state until a relatively long period has elapsed. This period is all the longer as the number of comparators is great. Consequently, in practice, the specialist cannot make parallel, fast analog/digital converters with more than 8 bits in MOS technology.
The invention makes it possible to overcome these problems unexpectedly through an operation which is no longer done in the usual way with in a single stage a, synchronous for all the comparators, but in stages a.sub.1, a.sub.2 . . . a.sub.p (p=2.sup.n) applied sequentially to one or more comparators at a time, without thereby causing any deterioration in the result of the conversion. Thus, the comparators continually give the position of the input signal Vin and logic data are taken at the rate of a clock which is independent of the stages a1, a2 . . . ap, each comparator having an auto zero stage proper to itself.